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PDF 74LVT573 Data sheet ( Hoja de datos )
| Número de pieza | 74LVT573 | |
| Descripción | Low Voltage Octal Transparent Latch with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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March 1999
Revised March 1999
74LVT573 • 74LVTH573
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVT573 and LVTH573 consist of eight latches with 3-
STATE outputs for bus organized system applications. The
latches appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is low, the data satisfying the input
timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The LVTH573 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal latches are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT573 and LVTH573
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH573), also
available without bushold feature (74LVT573).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 573
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVT573WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVT573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
74LVT573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVT573MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVTH573WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVTH573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
74LVTH573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH573MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS012450.prf
www.fairchildsemi.com
1 page  
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, .300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
Package Number M20D
5
www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74LVT573.PDF ] | |
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