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PDF 74LVTH322373 Data sheet ( Hoja de datos )
| Número de pieza | 74LVTH322373 | |
| Descripción | Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25ohm Series Resistors in the Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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May 2002
Revised May 2002
74LVT322373 • 74LVTH322373
Low Voltage 32-Bit Transparent Latch
with 3-STATE Outputs
and 25Ω Series Resistors in the Outputs
General Description
The LVT322373 and LVTH322373 contain thirty-two non-
inverting latches with 3-STATE outputs and are intended
for bus oriented applications. The device is byte controlled.
The flip-flops appear transparent to the data when the
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the setup time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the outputs are in a high impedance state.
The LVTH322373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT322373 and
LVTH322373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322373),
also available without bushold feature (74LVT322373)
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs include equivalent series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number Package Number
Package Description
74LVT322373G
(Note 1) (Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary)
74LVTH322373G
(Note 1) (Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering Code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500742
www.fairchildsemi.com
1 page  
DC Electrical Characteristics (Continued)
Symbol
Parameter
ICCZ+
Power Supply Current
(VCC1 or VCC2)
VCC T A = −40°C to +85°C Units
(V) Min Max
3.6
0.19
mA
∆ICC
Increase in Power Supply Current (VCC1 or VCC2)
(Note 7)
3.6
0.2 mA
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
One Input at VCC − 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 8)
Symbol
Parameter
VCC TA = 25°C
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
VOLV
Quiet Output Minimum Dynamic VOL
3.3
−0.8
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
Units
V
V
Conditions
CL = 50 pF, RL = 500Ω
(Note 9)
(Note 9)
AC Electrical Characteristics
TA = −40°C to +85°C, CL= 50pF, RL= 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.7V
Units
Min Max Min Max
tPHL Propagation Delay
tPLH
Dn to On
1.3 4.8 1.3 5.3
ns
1.4 4.8 1.4 5.1
tPHL Propagation Delay
tPLH
LE to On
1.7 5.0 1.7 5.1
ns
1.4 5.1 1.4 5.8
tPZL
tPZH
Output Enable Time
1.6 5.0 1.6 6.0
ns
1.0 5.4 1.0 6.6
tPLZ
tPHZ
Output Disable Time
1.6 5.1 1.6 5.0
ns
1.8 5.4 1.8 5.7
tS Setup Time, Dn to LE 1.0 0.8 ns
tH Hold Time, Dn to LE
1.0 1.1 ns
tW LE Pulse Width
3.0 3.0 ns
tOSHL
tOSLH
Output to Output Skew (Note 10)
1.0 1.0
ns
1.0 1.0
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 11)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = Open, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74LVTH322373.PDF ] | |
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| 74LVTH322373 | Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25ohm Series Resistors in the Outputs | Fairchild Semiconductor |
| 74LVTH322373G | Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25 Series Resistors in the Outputs | Fairchild Semiconductor |
| 74LVTH322374 | Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs and 25 Series Resistors in the Outputs (Preliminary) | Fairchild Semiconductor |
| 74LVTH322374GX | Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs and 25 Series Resistors in the Outputs (Preliminary) | Fairchild Semiconductor |
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