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Philips |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7597
8-bit shift register with input latches
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
8-bit shift register with input latches
Product specification
74HC/HCT7597
FEATURES
• 8-bit parallel input latches
• Shift register has direct overriding load and clear
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT7597 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT7597 both consist of an 8-bit storage latch
feeding a parallel-in, serial-out 8-bit shift register.
When LE is LOW, data at the Dn inputs enter the latches.
In this condition the latches are transparent, i.e. a latch
output will change state each time its corresponding
D-input changes.
When LE is HIGH the latches store the information that
was present at the D-inputs, a set-up time preceding the
LOW-to-HIGH transition of LE.
The shift register has a positive edge-triggered clock,
direct load (from storage) and clear inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
tPHL/ tPLH
fmax
CI
CPD
PARAMETER
CONDITIONS
propagation delay
SHCP to Q
LE to Q
PL to Q
D7 to Q
maximum clock frequency SHCP
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1, 2
TYPICAL
HC HCT
15 17
22 27
20 23
20 24
99 79
3.5 3.5
29 30
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF; VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V
UNIT
ns
ns
ns
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
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