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74HC573 반도체 회로 부품 판매점

Octal D-type transparent latch 3-state



Philips 로고
Philips
74HC573 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT573
Octal D-type transparent latch;
3-state
Product specification
File under Integrated Circuits, IC06
December 1990


74HC573 데이터시트, 핀배열, 회로
Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
74HC/HCT573
FEATURES
GENERAL DESCRIPTION
Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessors
Useful as input or output port for
microprocessors/microcomputers
3-state non-inverting outputs for
bus oriented applications
Common 3-state output enable
input
Functionally identical to the “563”
and “373”
Output capability: bus driver
ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
The 74HC/HCT573 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT573 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and 3-state outputs for bus oriented
applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
The “573” consists of eight D-type
transparent latches with 3-state true
outputs. When LE is HIGH, data at
the Dn inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
The “573” is functionally identical to
the “563” and “373”, but the “563” has
inverted outputs and the “373” has a
different pin arrangement.
SYMBOL
tPHL/ tPLH
CI
CPD
PARAMETER
CONDITIONS
propagation delay
Dn to Qn
LE to Qn
input capacitance
CL = 15 pF; VCC = 5 V
power dissipation capacitance per latch notes 1 and 2
TYPICAL
HC HCT
14 17
15 15
3.5 3.5
26 26
UNIT
ns
ns
pF
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi +(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF; VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2




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74HC573 latch

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