74FR573SC 반도체 회로 부품 판매점
Octal D-Type Latch with 3-STATE Outputs
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 Fairchild |
January 1991
Revised August 1999
74FR573
Octal D-Type Latch with 3-STATE Outputs
General Description
The 74FR573 is a high speed octal latch with buffered
common Latch Enable (LE) and buffered common Output
Enable (OE) inputs.
This device is functionally identical to the 74F573.
Features
s Broadside pinout aids in PC layout
s Functionally identical to the 74F373, 74F573
s Outputs have current sourcing capability of 15 mA and
current sinking capability of 64 mA
s Guaranteed pin-to-pin skew
Ordering Code:
Order Number Package Number
Package Description
74FR573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74FR573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
LE
D0–D7
O0–O7
Description
Output Enable Input (Active-LOW)
Latch Enable Input (Active-HIGH)
Data Inputs
3-STATE Latch Outputs
© 1999 Fairchild Semiconductor Corporation DS010903
www.fairchildsemi.com
Functional Description
The 74FR573 contains eight D-type latches with 3-STATE
output buffers. When the latch enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode, but this does not interfere with entering
new data into the latches.
Function Table
Inputs
OE LE
LH
LH
LL
HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Dn
H
L
X
X
Logic Diagram
Output
On
H
L
On − 1
High Z State
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74FR573SC latch
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