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74F374 반도체 회로 부품 판매점

Octal transparent latch 3-State



Philips 로고
Philips
74F374 데이터시트, 핀배열, 회로
FAST PRODUCTS
74F373
Octal transparent latch (3-State)
74F374
Octal D flip-flop (3-State)
Product specification
IC15 Data Handbook
Philips Semiconductors
1994 Dec 05


74F374 데이터시트, 핀배열, 회로
Philips Semiconductors
Latch/flip-flop
Product specification
74F373/74F374
74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
FEATURES
8-bit transparent latch — 74F373
8-bit positive edge triggered register — 74F374
3-State outputs glitch free during power-up and power-down
Common 3-State output register
Independent register and 3-State buffer operation
SSOP Type II Package
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is high. The latch remains transparent to the data
input while E is high, and stores the data that is present one setup
time before the high-to-low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is low, latched or
transparent data appears at the output.
When OE is high, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the low-to-high clock transition is transferred to the
corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active low output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is low, the data in
the register appears at the outputs. When OE is high, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
TYPE
74F373
TYPICAL
PROPAGATION
DELAY
4.5ns
TYPICAL SUPPLY
CURRENT
(TOTAL)
35mA
TYPE
74F374
TYPICAL fmax
165MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
55mA
ORDERING INFORMATION
DESCRIPTION
20-pin plastic DIP
20-pin plastic SOL
20-pin plastic SSOP type II
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F373N, N74F374N
N74F373D, N74F374D
N74F373DB, N74374DB
PKG DWG #
SOT146-1
SOT163-1
SOT399-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
D0 - D7
Data inputs
1.0/1.0
E (74F373)
Enable input (active high)
1.0/1.0
OE Output enable inputs (active low)
1.0/1.0
CP (74F374)
Clock pulse input (active rising edge)
1.0/1.0
Q0 - Q7
3-State outputs
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
December 5, 1994
2
853-0369 14383




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74F374 latch

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