74VHCT373AT 반도체 회로 부품 판매점
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
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 STMicroelectronics |
® 74VHCT373A
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.9V (Max.)
DESCRIPTION
The 74VHCT373A is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHCT373AM
74VHCT373AT
(OE).
While the LE input is held at a high level, the Q
outputs will follow the data inputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
November 1999
1/10
74VHCT373A
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 5, 6,
9, 12, 15,
16, 19
3, 4, 7,
8, 13, 14,
17, 18
11
10
20
S Y M B OL
OE
Q0 to Q7
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
3 State Outputs
D0 to D7 Data Inputs
LE
GND
VCC
Latch Enable
Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OE LE
D
HXX
LLX
LHL
L HH
X:DON’T CARE
Z: HIGH IMPEDANCE
*: Q OUTPUTSARE LATCHED AT THE TIME WHEN THE LEINPUT ISTAKEN LOW LOGIC LEVEL.
OUT PUTS
Q
Z
NO CHANGE *
L
H
LOGIC DIAGRAM
2/10
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( stm )
74VHCT373AT latch
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국내 전력반도체 판매점
상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
[ 홈페이지 ]
IGBT, TR 모듈, SCR, 다이오드모듈, 각종 전력 휴즈
( IYXS, Powerex, Toshiba, Fuji, Bussmann, Eaton )
전력반도체 문의 : 010-3582-2743
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