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Fairchild Semiconductor |
May 1998
74LVQ573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVQ573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output Enable
(OE) inputs. The LVQ573 is functionally identical to the
LVQ373 but with inputs and outputs on opposite sides of the
package.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ, and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75Ω
n 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ573SC
74LVQ573SJ
74LVQ573QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for
SOIC and QSOP
DS011361-1
IEEE/IEC
DS011361-2
DS011361-3
Pin Descriptions
Pin Names
D0– D7
LE
OE
O0– O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
© 1998 Fairchild Semiconductor Corporation DS011361
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Truth Table
Inputs
Outputs
OE LE D
L HH
On
H
L HL
L
L LX
H XX
O0
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Functional Description
The LVQ573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D-type input changes. When LE is LOW the
latches store the information that was present on the D-type
inputs a setup time preceding the HIGH-to-LOW transition of
LE. The 3-STATE buffers are controlled by the Output En-
able (OE) input. When OE is LOW, the buffers are enabled.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
DS011361-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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