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PDF 74LVC573A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC573A | |
| Descripción | Octal D-type transparent latch | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74LVC573A
Octal D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 5 — 19 February 2013
Product data sheet
1. General description
The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type
inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch
Enable (LE) input and an Output Enable (OE) input are common to all internal latches.
When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches
are transparent, that is, a latch output changes each time its corresponding D-input
changes. When LE is LOW, the latches store the information that was present at the
D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the outputs. When OE
is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does
not affect the state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V or 5 V applications.
The 74LVC573A is functionally identical to the 74LVC373A, but has a different pin
arrangement.
2. Features and benefits
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when VCC = 0 V
Flow-through pinout architecture
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
1 page  
NXP Semiconductors
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description
Table 3. Functional table[1]
Operating modes
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable outputs
Input
OE
L
L
L
L
H
H
LE
H
H
L
L
L
L
Dn
L
H
l
h
l
h
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high-impedance OFF-state
7. Limiting values
Internal latch Output
Qn
LL
HH
LL
HH
LZ
HZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max
Unit
VCC
IIK
VI
IOK
VO
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0
VO > VCC or VO < 0
VO = 0 V to VCC
Tamb = 40 C to +125 C
0.5
50
[1] 0.5
-
[2] 0.5
-
-
100
65
[3] -
+6.5
-
+6.5
50
VCC + 0.5
50
100
-
+150
500
V
mA
V
mA
V
mA
mA
mA
C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 and DHXQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
74LVC573A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 19 February 2013
© NXP B.V. 2013. All rights reserved.
5 of 20
5 Page 
NXP Semiconductors
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
tW
VM
tr
tf
VM
VI
G
VCC
DUT
VO
VEXT
RL
RT CL RL
001aae331
Test data is given in Table 9. Definitions for test circuit:
RL = Load resistance. CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 11. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
1.2 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
Input
VI
VCC
VCC
VCC
2.7 V
2.7 V
tr, tf
2 ns
2 ns
2 ns
2.5 ns
2.5 ns
Load
CL
30 pF
30 pF
30 pF
50 pF
50 pF
RL
1 k
1 k
500
500
500
VEXT
tPLH, tPHL
open
open
open
open
open
tPLZ, tPZL
2 VCC
2 VCC
2 VCC
2 VCC
2 VCC
tPHZ, tPZH
GND
GND
GND
GND
GND
74LVC573A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 19 February 2013
© NXP B.V. 2013. All rights reserved.
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