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74LV595 반도체 회로 부품 판매점

8-bit serial-in/serial or parallel-out shift register with output latches 3-State



Philips 로고
Philips
74LV595 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74LV595
8-bit serial-in/serial or parallel-out shift
register with output latches (3-State)
Product specification
IC24 Data Handbook
1998 Apr 20
Philips
Semiconductors


74LV595 데이터시트, 핀배열, 회로
Philips Semiconductors
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
Product specification
74LV595
FEATURES
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V,
Tamb = 25°C
Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V,
Tamb = 25°C
8-bit serial input
8-bit serial or parallel output
Storage register with 3-State outputs
Shift register with direct clear
Output capability:
– parallel outputs; bus driver
– serial output; standard
ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register
DESCRIPTION
The 74LV595 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT595.
The74LV595 is an 8-stage serial shift register with a storage register
and 3-State outputs. The shift register and storage register have
separate clocks.
Data is shifted on the positive-going transitions of the SHCP input.
The data in each register is transferred to the storage register on a
positive-going transition of the STCP input. If both clocks are
connected together, the shift register will always be one clock pulse
ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output
(Q7’) all for cascading. It is also provided with asynchronous reset
(active LOW) for all 8 shift register stages. The storage register has
8 parallel 3-State bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is
LOW.
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
fmax
CI
CPD
Propagation delay
SHCP to Q7’
STCP to Q7’
MR to Q7’
Maximum clock frequency SHCP, STCP
Input capacitance
Power dissipation capacitance per gate
CL = 15pF
VCC= 3.3V
VCC = 3.3V
Notes 1 and 2
15
16
ns
14
77 MHz
3.5 pF
115 pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
16-Pin Plastic DIL
–40°C to +125°C
16-Pin Plastic SO
–40°C to +125°C
16-Pin Plastic SSOP Type II
–40°C to +125°C
16-Pin Plastic TSSOP Type I
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV595 N
74LV595 D
74LV595 DB
74LV595 PW
NORTH AMERICA
74LV595 N
74LV595 D
74LV595 DB
74LV595PW DH
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
1998 Apr 20
2 853-1987 19255




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74LV595

8-bit serial-in/serial or parallel-out shift register with output latches 3-State - Philips