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74LCXH16373MTD 반도체 회로 부품 판매점

Low Voltage 16-Bit Transparent Latch with Bushold



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LCXH16373MTD 데이터시트, 핀배열, 회로
February 2001
Revised August 2001
74LCXH16373
Low Voltage 16-Bit Transparent Latch with Bushold
General Description
The LCXH16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCXH16373 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCXH16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
The LCXH16373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data input at a valid logic level.
Features
I 5V tolerant control inputs and outputs
I 2.3V–3.6V VCC specifications provided
I 5.4 ns tPD max (VCC = 3.3V), 20 µA ICC max
I Bushold on inputs eliminates the need for external
pull-up/pull-down resistors
I Power down high impedance outputs
I ±24 mA output drive (VCC = 3.0V)
I Implements patented noise/EMI reduction circuitry
I Latch-up performance exceeds 500 mA
I ESD performance:
Human body model > 2000V
Machine model > 200V
I Also available in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number Package Number
Package Description
74LCXH16373GX
(Note 1)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LCXH16373MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCXH16373MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500440
www.fairchildsemi.com


74LCXH16373MTD 데이터시트, 핀배열, 회로
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
Pin Names
Description
OEn
LEn
I0I15
O0O15
NC
Output Enable Input (Active LOW)
Latch Enable Input
Bushold Inputs
Outputs
No Connect
FBGA Pin Assignments
12
A O0 NC
B O2 O1
C O4 O3
D O6 O5
E O8 O7
F O10 O9
G O12 O11
H O14 O13
J O15 NC
Truth Tables
3
OE1
NC
VCC
GND
GND
GND
VCC
NC
OE2
4
LE1
NC
VCC
GND
GND
GND
VCC
NC
LE2
5
NC
I1
I3
I5
I7
I9
I11
I13
NC
6
I0
I2
I4
I6
I8
I10
I12
I14
I15
Inputs
Outputs
LE1 OE1
XH
HL
HL
LL
I0–I7
X
L
H
X
O0–O7
Z
L
H
O0
Inputs
Outputs
LE2 OE2
I8–I15
O8–O15
XH
X
Z
HL
L
L
HL
H
H
LL
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
www.fairchildsemi.com
2




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Low Voltage 16-Bit Transparent Latch with Bushold - Fairchild Semiconductor