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Fairchild Semiconductor |
February 2006
74LCX373
Low Voltage Octal Transparent Latch
with 5V Tolerant Inputs and Outputs
Features
■ 5V tolerant inputs and outputs
■ 2.3V–3.6V VCC specifications provided
■ 8.0ns tPD max (VCC = 3.3V), 10µA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal1
■ ±24mA output drive (VCC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance
– Human body model > 2000V
– Machine model > 200V
■ Leadless Pb-Free DQFN package
General Description
The LCX373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The device is
designed for low voltage applications with capability of
interfacing to a 5V signal environment.
The LCX373 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Order
Number
74LCX373WM
74LCX373SJ
74LCX373BQX2
74LCX373MSA
74LCX373MTC
74LCX373MTCX_NL3
Package
Number
M20B
M20D
MLP020B
MSA20
MTC20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads
(DQFN), JEDEC MO-241, 2.5 x 4.5mm
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm
Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Notes:
1. To ensure the high impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum
value of the resistor is determined by the current-sourcing capability of the driver.
2. DQFN package available in Tape and Reel only.
3. “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
©2006 Fairchild Semiconductor Corporation
74LCX373 Rev. 2.0.0
1
www.fairchildsemi.com
Logic Symbols
D0 D1 D2 D3 D4 D5 D6 D7
LE
OE
O0 O1 O2 O3 O4 O5 O6 O7
IEEE/IEC
OE EN
LE C1
D0 1D
D1
D2
D3
D4
D5
D6
D7
O0
O1
O2
O3
O4
O5
O6
O7
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
OE
O0
D0
D1
O1
O2
D2
D3
O3
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 O7
18 D7
17 D6
16 O6
15 O5
14 D5
13 D4
12 O4
11 LE
Pad Assignments for DQFN
OE VCC
1 20
O0 2
19 O7
D0 3
18 D7
D1 4
17 D6
O1 5
16 O6
O2 6
15 O5
D2 7
14 D5
D3 8
13 D4
O3 9
12 O4
10 11
GND LE
(Top View)
74LCX373 Rev. 2.0.0
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Truth Table
Inputs
Outputs
LE OE Dn
X HX
On
Z
H LL
L
H LH
H
L LX
O0
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch
Enable
Functional Description
The LCX373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this
condition the latches are transparent, i.e. a latch output
will change state each time its D input changes. When
LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2-state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
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