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PDF 74HCT595 Data sheet ( Hoja de datos )

Número de pieza 74HCT595
Descripción 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state
Fabricantes Philips 
Logotipo Philips Logotipo



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No Preview Available ! 74HCT595 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jun 04

1 page




74HCT595 pdf
Philips Semiconductors
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
Product specification
74HC/HCT595
handbook, full pagewidth
DS
SHCP
MR
STCP
OE
STAGE 0
DQ
FF0
CP
R
STAGES 1 TO 6
DQ
STAGE 7
DQ
FF7
CP
R
Q7'
DQ
LATCH
CP
DQ
LATCH
CP
Q0 Q1 Q2 Q3 Q4 Q5 Q6
Fig.5 Logic diagram.
Q7 MLA010
1998 Jun 04
5

5 Page





74HCT595 arduino
Philips Semiconductors
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
Product specification
74HC/HCT595
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
TEST CONDITION
SYMBOL PARAMETER
min
+25
typ max
40 to +85
min max
40 to +125
min max
UNIT
VCC
(V)
WAVEFORMS
tPHL/ tPLH
tPHL/ tPLH
tPHL
tPZH/ tPZL
tPHZ/ tPLZ
tW
propagation delay
SHCP to Q7
propagation delay
STCP to Qn
propagation delay
MR to Q7
3-state output enable
time OE to Qn
3-state output disable
time OE to Qn
shift clock pulse
width HIGH or LOW
25 42
24 40
23 40
21 35
18 30
16 6
tW storage clock pulse width 16 5
HIGH or LOW
tW master reset
pulse width LOW
20 8
tsu set-up time DS to
SHSP
16 5
tsu set-up time SHCP
to STCP
16 8
th
hold time DS to SHCP
3 2
53
50
50
44
38
20
20
25
20
20
3
63
60
60
53
45
24
24
30
24
24
3
ns 4.5 Fig.7
ns 4.5 Fig.8
ns 4.5 Fig.10
ns 4.5 Fig.11
ns 4.5 Fig.11
ns 4.5 Fig.7
ns 4.5 Fig.8
ns 4.5 Fig.10
ns 4.5 Fig.9
ns 4.5 Fig.8
ns 4.5 Fig.9
trem removal time MR
to SHCP
fmax maximum clock
pulse frequency
SHCP or STCP
10 7
30 52
13
24
15
20
ns 4.5 Fig.10
MHz 4.5 Figs 7 and 8
1998 Jun 04
11

11 Page







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