|
STMicroelectronics |
74AC573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED: tPD = 4.5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s 50Ω TRANSMISSION LINE DRIVING
BM
CAPABILITY
(Plastic Package)
(Micro Package)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s IMPROVED LATCH-UP IMMUNITY
ORDER CODES :
74AC573B
74AC573M
latch enable input (LE) and an output enable
input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
DESCRIPTION
While the (OE) input is low, the 8 outputs will be
The AC573 is an advanced high-speed CMOS in a normal logic state (high or low logic level)
OCTAL D-TYPE LATCH with 3 STATE OUTPUT andwww.DataSheet4U.com while high level the outputs will be in a high
NON INVERTING fabricated with sub-micron impedance state.
silicon gate and double-layer metal wiring C2MOS All inputs and outputs are equipped with
technology. It is ideal for low power applications protection circuits against static discharge, giving
mantaining high speed operation similar to them 2KV ESD immunity and transient excess
equivalent Bipolar Schottky TTL.
voltage.
These 8 bit D-Type latches are controlled by a
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
1/10
74AC573
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 3, 4,
5, 6, 7,
8, 9
12, 13, 14,
15, 16, 17,
18, 19
11
10
20
SYMBOL
OE
D0 to D7
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
Data Inputs
Q0 to Q7 3 State Latch Outputs
LE
GND
VCC
Latch Enable
Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
IN PUT S
OE LE
HX
LL
LH
LH
X: Don’t care
Z: High impedance
* Q output are latched at the time when the LE inputs taken low logic level.
D
X
X
L
H
OUTPUTS
Q
Z
NO CHANGE *
L
H
LOGIC DIAGRAM
2/10
|