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74ABT573CMTC 반도체 회로 부품 판매점

Octal D-Type Latch with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ABT573CMTC 데이터시트, 핀배열, 회로
January 1993
Revised November 1999
74ABT573
Octal D-Type Latch with 3-STATE Outputs
General Description
The ABT573 is an octal latch with buffered common Latch
Enable (LE) and buffered common Output Enable (OE)
inputs.
This device is functionally identical to the ABT373 but has
broadside pinouts.
Features
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Useful as input or output port for microprocessors
s Functionally identical to ABT373
s 3-STATE outputs for bus interfacing
s Output sink capability of 64 mA, source capability of
32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch-free bus loading during entire
power up and power down
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT573CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body
74ABT573CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT573CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT573CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT573CPC
N20A
20-Lead Plastic Dual-In-Line (PDIP), JEDEC MS-01, 0.300Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0D7
LE
OE
O0O7
Descriptions
Data Inputs
Latch Enable Input (Active HIGH)
3-STATE Output Enable Input (Active LOW)
3-STATE Latch Outputs
© 1999 Fairchild Semiconductor Corporation DS011548
www.fairchildsemi.com


74ABT573CMTC 데이터시트, 핀배열, 회로
Functional Description
The ABT573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Logic Diagram
Function Table
Inputs
OE LE D
L HH
L HL
L LX
H XX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
O0 = Value stored from previous clock cycle
Outputs
O
H
L
O0
Z
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ABT573CMTC latch

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Octal D-Type Latch with 3-STATE Outputs - Fairchild Semiconductor