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PDF 74ABT373CPC Data sheet ( Hoja de datos )
| Número de pieza | 74ABT373CPC | |
| Descripción | Octal Transparent Latch with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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January 1993
Revised November 1999
74ABT373
Octal Transparent Latch with 3-STATE Outputs
General Description
The ABT373 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
Features
s 3-STATE outputs for bus interfacing
s Output sink capability of 64 mA, source capability of
32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT373CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT373CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT373CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT373CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT373CPC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-STATE Latch Outputs
© 1999 Fairchild Semiconductor Corporation DS011547
www.fairchildsemi.com
1 page  
Extended AC Electrical Characteristics
(SOIC Package)
TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
VCC = 4.5V to 5.5V
Symbol
Parameter
CL = 50 pF
8 Outputs Switching
CL = 250 pF
CL = 250 pF
8 Outputs Switching
Units
(Note 8)
(Note 9)
(Note 10)
Min Max Min Max Min Max
tPLH Propagation Delay
1.5 5.2 2.0 6.8 2.0 9.0
tPHL
Dn to On
1.5 5.2 2.0 6.8 2.0 9.0
tPLH Propagation Delay
1.5 5.5 2.0 7.5 2.0 9.5
tPHL
LE to On
1.5 5.5 2.0 7.5 2.0 9.5
tPZH Output Enable Time
1.5 6.2 2.0 8.0 2.0 10.5
tPZL 1.5 6.2 2.0 8.0 2.0 10.5
tPHZ
tPZL
Output Disable Time
1.0 5.5
1.0 5.5
(Note 11)
(Note 11)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
ns
ns
ns
ns
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Skew
(SOIC Package)
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
Symbol
Parameter
CL = 50 pF
8 Outputs Switching
CL = 250 pF
8 Outputs Switching
Units
(Note 12)
(Note 13)
Max
Max
tOSHL (Note 14) Pin to Pin Skew, HL Transitions
1.0
1.5 ns
tOSLH (Note 14) Pin to Pin Skew, LH Transitions
1.0
1.5 ns
tPS (Note 16)
Duty Cycle, LH–HL Skew
1.4 3.5 ns
tOST (Note 14) Pin to Pin Skew, LH/HL Transitions
1.5
3.9 ns
tPV (Note 15)
Device to Device Skew, LH/HL Transitions
2.0
4.0 ns
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or
HIGH-to-LOW (tOST). This specification is guaranteed but not tested.
Note 15: Propagation delay variation is for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but
not tested.
Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Symbol
Parameter
Typ
CIN
COUT (Note 17)
Input Capacitance
Output Capacitance
5
9
Note 17: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Units
pF
pF
VCC = 0V
VCC = 5.0V
Conditions
(TA = 25°C)
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
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