74ALVCH16843DGG 반도체 회로 부품 판매점
18-bit bus-interface D-type latch 3-State
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 NXP Semiconductors |
INTEGRATED CIRCUITS
74ALVCH16843
18-bit bus-interface D-type latch (3-State)
Product specification
IC24 Data Handbook
1998 Aug 04
Philips
Semiconductors
Philips Semiconductors
18-bit bus interface D-type latch (3-State)
Product specification
74ALVCH16843
FEATURES
• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
• All data inputs have bus hold
• Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16843 has two 9–bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE), clear (nCLR),
preset (nPRE) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appear at the outputs.
When nOE is HIGH, the outputs are in the high impedance OFF
state. Operation of the nOE input does not affect the state of the
flip-flops.
The 74ALVCH16843 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1CLR
1OE
1Q0
GND
1Q1
1Q2
VCC
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
VCC
2Q6
2Q7
GND
2Q8
2OE
2CLR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 1LE
55 1PRE
54 1D0
53 GND
52 1D1
51 1D2
50 VCC
49 1D3
48 1D4
47 1D5
46 GND
45 1D6
44 1D7
43 1D8
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
35 VCC
34 2D6
33 2D7
32 GND
31 2D8
30 2PRE
29 2LE
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
SH00143
TYPICAL
tPHL/tPLH
CI
Propagation delay
nDn to nQn
Propagation delay
nLE to nQn
Input capacitance
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
transparent mode
Output enabled
Output disabled
Clocked mode
Output enabled
Output disabled
2.2
2.1
2.3
2.0
5.0
17
3
19
9
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
ns
pF
pF
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
TEMPERATURE
RANGE
–40°C to +85°C
OUTSIDE NORTH
AMERICA
74ALVCH16843 DGG
NORTH AMERICA
ACH16843 DGG
DRAWING
NUMBER
SOT364-1
1998 Aug 04
2 853–2108 019833
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74ALVCH16843DGG latch
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