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PDF 74ALVC16841MTD Data sheet ( Hoja de datos )
| Número de pieza | 74ALVC16841MTD | |
| Descripción | Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 2001
Revised November 2001
74ALVC16841
Low Voltage 20-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The 74ALVC16841 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC16841 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I 1.65V–3.6V VCC supply operation
I 3.6V tolerant inputs and outputs
I tPD (Dn to On)
3.5 ns max for 3.0V to 3.6V VCC
3.9 ns max for 2.3V to 2.7V VCC
6.8 ns max for 1.65V to 1.95V VCC
I Power-off high impedance inputs and outputs
I Supports live insertion and withdrawal (Note 1)
I Uses patented noise/EMI reduction circuitry
I Latchup conforms to JEDEC JED78
I ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC16841MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
LEn
D0–D19
O0–O19
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS500690
www.fairchildsemi.com
1 page  
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
VL
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
Symbol
Vmi
Vmo
VX
VY
VL
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
1.8V ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
trec Waveforms
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
5 www.fairchildsemi.com
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74ALVC16841MTD.PDF ] | |
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