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Fairchild Semiconductor |
March 1990
Revised December 1998
74ACTQ843
Quiet Series™ 9-Bit Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths. The
ACTQ843 utilizes Fairchild FACT Quiet Series™ technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO™ output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Inputs and outputs on opposite sides of package for
easy interface with microprocessors
s Improved latch-up immunity
s Outputs source/sink 24 mA
s ACTQ843 has TTL-compatible inputs
s Functionally and pin-compatible to AMD’s AM29843
s 3-STATE outputs for bus interfacing
Ordering Code:
Order Number Package Number
Package Description
74ACTQ843SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ843SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for DIP and SOIC
Pin Descriptions
Pin Names
D0–D8
O0–O8
OE
LE
CLR
PRE
Description
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
Preset
FACT™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010689.prf
www.fairchildsemi.com
Functional Description
The ACTQ843 consists of nine D-type latches with 3-
STATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asyn-
chronous operation, as the output transition follows the
data in transition. On the LE HIGH-to-LOW transition, the
data that meets the setup times is latched. Data appears
on the bus when the Output Enable (OE) is LOW. When
OE is HIGH, the bus output is in the high impedance state.
Function Table
In addition to the LE and OE pins, the ACTQ843 has a
Clear (CLR) pin and a Preset (PRE) pin. These pins are
ideal for parity bus interfacing in high performance sys-
tems. When CLR is LOW, the outputs are LOW if OE is
LOW. When CLR is HIGH, data can be entered into the
latch. When PRE is LOW, the outputs are HIGH if OE is
LOW. Preset overrides CLR.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Inputs
Internal Outputs
Function
CLR PRE OE LE D
Q
O
HHHH L
L
Z High Z
HHHHH
H
Z High Z
HHHL X
NC
Z Latched
HH L H L
L
L Transparent
HH L HH
H
H Transparent
HHL L X
NC
NC Latched
HL LXX
H
H Preset
LHLXX
L
L Clear
L L LXX
H
H Preset
LHHL X
L
Z Clear/High Z
HLHLX
H
Z Preset/High Z
Logic Diagram
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