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74ACTQ533PC 반도체 회로 부품 판매점

Quiet Series Octal Transparent Latch with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ACTQ533PC 데이터시트, 핀배열, 회로
January 1990
Revised November 1999
74ACTQ533
Quiet Series Octal Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ533 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data satisfying the input tim-
ing requirements is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high impedance state.
The ACTQ533 utilizes Fairchild Quiet Seriestechnology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
Features
s ICC and IOZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch up immunity
s Eight latches in a single package
s 3-STATE outputs drive bus lines or buffer memory
address registers
s Outputs source/sink 24 mA
s Inverted version of the ACTQ373
s 4 kV minimum ESD immunity
Ordering Code:
Order Number Package Number
Package Description
74ACTQ533SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body
74ACTQ533MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ533PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0D7
LE
Data Inputs
Latch Enable Input
OE Output Enable Input
O0O7
3-STATE Latch Outputs
FACT, FACT Quiet Series, and GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010630
www.fairchildsemi.com


74ACTQ533PC 데이터시트, 핀배열, 회로
Truth Table
Inputs
LE OE
XH
HL
HL
LL
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Dn
X
L
H
X
Outputs
On
Z
H
L
O0
Functional Description
The ACTQ533 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs at setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE standard outputs are con-
trolled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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Quiet Series Octal Transparent Latch with 3-STATE Outputs - Fairchild Semiconductor