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74ACT843SC 반도체 회로 부품 판매점

9-Bit Transparent Latch



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ACT843SC 데이터시트, 핀배열, 회로
July 1988
Revised September 2000
74ACT843
9-Bit Transparent Latch
General Description
The ACT843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths.
Features
s TTL compatible inputs
s 3-STATE outputs for bus interfacing
Ordering Code:
Order Number Package Number
Package Description
74ACT843SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT843SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0D8
O0O8
OE
LE
CLR
PRE
Description
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
Preset
FACTis a trademark of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation DS009800
www.fairchildsemi.com


74ACT843SC 데이터시트, 핀배열, 회로
Functional Description
The ACT843 consists of nine D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion. On the LE HIGH-to-LOW transition, the data that
meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state. In addition to
Function Tables
the LE and OE pins, the ACT843 has a Clear (CLR) pin
and a Preset (PRE) pin. These pins are ideal for parity bus
interfacing in high performance systems. When CLR is
LOW, the outputs are LOW if OE is LOW. When CLR is
HIGH, data can be entered into the latch. When PRE is
LOW, the outputs are HIGH if OE is LOW. Preset overrides
CLR.
Inputs
CLR
H
H
H
H
H
H
H
L
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
PRE
H
H
H
H
H
H
L
H
L
H
L
OE
H
H
H
L
L
L
L
L
L
H
H
LE
H
H
L
H
H
L
X
X
X
L
L
D
L
H
X
L
H
X
X
X
X
X
X
Internal
Q
L
H
NC
L
H
NC
H
L
H
L
H
Outputs
O
Z
Z
Z
L
H
NC
H
L
H
Z
Z
Function
High Z
High Z
Latched
Transparent
Transparent
Latched
Preset
Clear
Preset
Clear/High Z
Preset/High Z
Logic Diagram
www.fairchildsemi.com
2




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74ACT843SC latch

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