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Fairchild Semiconductor |
November 1988
Revised September 2000
74ACT841
10-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACT841 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The ACT841 is a 10-bit transparent
latch, a 10-bit version of the ACT373.
Features
s ACT841 has TTL-compatible inputs
s Outputs source/sink 24 mA
s Non-inverting 3-STATE outputs
Ordering Code:
Order Number Package Number
Package Description
74ACT841SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT841MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT841SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D9
O0–O9
OE
LE
Description
Data Inputs
3-STATE Outputs
Output Enable
Latch Enable
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010156
www.fairchildsemi.com
Functional Description
The ACT841 consists of ten D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH
the bus output is in the high impedance state.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
OE
X
H
H
H
L
L
L
Logic Diagram
Inputs
LE
X
H
H
L
H
H
L
D
X
L
H
X
L
H
X
Internal
Q
X
L
H
NC
L
H
NC
Output
O
Z
Z
Z
Z
L
H
NC
Function
High Z
High Z
High Z
Latched
Transparent
Transparent
Latched
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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