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PDF 74ACT373SJ Data sheet ( Hoja de datos )
| Número de pieza | 74ACT373SJ | |
| Descripción | Octal Transparent Latch with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 1988
Revised November 1999
74AC373 • 74ACT373
Octal Transparent Latch with 3-STATE Outputs
General Description
The AC/ACT373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The flip-
flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
s ICC and IOZ reduced by 50%
s Eight latches in a single package
s 3-STATE outputs for bus interfacing
s Outputs source/sink 24 mA
s ACT373 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC373SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC373PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT373SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT373MSA
74ACT373MTC
MSA20
MTC20
20-Lead Shrink Swmwwa.lDl aOtauSthlieneet4UP.caocmkage (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT373PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering information
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009958
www.fairchildsemi.com
1 page  
AC Operating Requirements for AC
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to LE
tH Hold Time, HIGH or LOW
Dn to LE
tW LE Pulse Width,
HIGH
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
AC Electrical Characteristics for ACT
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
3.5 5.5
6.0
2.0 4.0
4.5
−3.0
1.0
1.0
−1.5
1.0
1.0
4.0 5.5
6.0
2.0 4.0
4.5
Units
ns
ns
ns
Symbol
Parameter
tPLH Propagation Delay
Dn to On
tPHL Propagation Delay
Dn to On
tPLH Propagation Delay
LE to On
tPHL Propagation Delay
LE to On
tPZH Output Enable Time
tPZL Output Enable Time
tPHZ Output Disable Time
tPLZ Output Disable Time
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 9)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Min
2.5
2.0
2.5
2.0
2.0
2.0
2.5
1.5
AC Operating Requirements for ACT
TA = +25°C
CL = 50 pF
Typ
8.5
8.0
8.5
8.0
8.0
7.5
9.0
7.5
Max
10.0
10.0
11.0
10.0
9.5
9.0
11.0
8.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
1.5 11.5
1.5 11.5
2.0 11.5
1.5 11.5
1.5 10.5
1.5 10.5
2.5 12.5
1.0 10.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to LE
tH Hold Time, HIGH or LOW
Dn to LE
tW LE Pulse Width, HIGH
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
VCC
(V)
(Note 10)
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Typ
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
0.8 2.5
3.5
00
2.0 7.0
1.0
8.0
Units
ns
ns
ns
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5
40.0
pF VCC = OPEN
pF VCC = 5.0V
5 www.fairchildsemi.com
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