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Fairchild Semiconductor |
August 1999
Revised October 1999
74ACT16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACT16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is low, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state.
Features
s Separate control logic for each byte
s 16-bit version of the ACT373
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT16373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
LEn
I0–I15
O0–O15
Description
Output Enable Input (Active Low)
Latch Enable Input
Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS500297
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Functional Description
The ACT16373 contains sixteen D-type latches with 3-
STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the Dn enters the latches. In this condition the latches are
transparent, i.e., a latch output will change states each time
its D input changes. When LEn is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The 3-
STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard out-
puts are in the 2-state mode. When OEn is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Logic Diagrams
Truth Tables
Inputs
LE1 OE1
XH
HL
HL
I0–I7
X
L
H
LL
X
Outputs
O0–O7
Z
L
H
(Previous)
Inputs
Outputs
LE2 OE2
XH
I8–I15
X
O8–O15
Z
HL
L
L
HL
H
H
LL
X (Previous)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Previous = previous output prior to HIGH-to-LOW transition of LE
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