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BH16373BDL 반도체 회로 부품 판매점

16-bit transparent latch 3-State



NXP Semiconductors 로고
NXP Semiconductors
BH16373BDL 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
Product specification
Supersedes data of 1995 Aug 03
IC23 Data Handbook
1998 Feb 27
Philips
Semiconductors


BH16373BDL 데이터시트, 핀배열, 회로
Philips Semiconductors
16-bit transparent latch (3-State)
Product specification
74ABT16373B
74ABTH16373B
FEATURES
16-bit transparent latch
Multiple VCC and GND pins minimize switching noise
Power-up 3-State
Live insertion/extraction permitted
Power-up reset
3-State output buffers
74ABTH16373B incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Output capability: +64mA/–32mA
ICCL –19 mA maximum
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE) control gates.
The data on each set of D inputs are transferred to the latch outputs
when the Latch Enable (nE) input is High. The latch remains
transparent to the data inputs while nE is High, and stores the data
that is present one setup time before the High-to-Low enable
transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-Low Output Enable (nOE) controls eight 3-State buffers
independent of the latch operation.
When nOE is Low, the latched or transparent data appears at the
outputs. When nOE is High, the outputs are in the High-impedance
“OFF” state, which means they will neither drive nor load the bus.
Two options are available, 74ABT16373B which does not have the
bus-hold feature and 74ABTH16373B which incorporates the
bus-hold feature.
PIN CONFIGURATION
1OE 1
1Q0 2
1Q1 3
GND 4
1Q2 5
1Q3 6
VCC 7
1Q4 8
1Q5 9
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
VCC 18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
48 1E
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 VCC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 VCC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2E
SA00379
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
ICCL
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Quiescent supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
VO = 0V or VCC; 3-State
Outputs disabled; VCC = 5.5V
Outputs low; VCC = 5.5V
TYPICAL
2.5
2.0
4
7
500
8
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
48-Pin SSOP type III
48-Pin TSSOP type II
48-Pin SSOP type III
48-Pin TSSOP type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT16373B DL
–40°C to +85°C
74ABT16373B DGG
–40°C to +85°C
74ABTH16373B DL
–40°C to +85°C
74ABTH16373B DGG
NORTH AMERICA
BT16373B DL
BT16373B DGG
BH16373B DL
BH16373B DGG
DWG NUMBER
SOT370-1
SOT362-1
SOT370-1
SOT362-1
1998 Feb 27
2 853-1751 19027




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16-bit transparent latch 3-State - NXP Semiconductors



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