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74LS256 반도체 회로 부품 판매점

DUAL 4-BIT ADDRESSABLE LATCH



Motorola Semiconductors 로고
Motorola Semiconductors
74LS256 데이터시트, 핀배열, 회로
DUAL 4-BIT
ADDRESSABLE LATCH
The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control
inputs; these include two Address inputs (A0, A1), an active LOW Enable input
(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and
four outputs (Q0 – Q3).
When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs
(Q0 – Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and
E are both LOW. When CL is HIGH and E is LOW, the selected output
(Q0 – Q3), determined by the Address inputs, follows D. When the E goes
HIGH, the contents of the latch are stored. When operating in the addressable
latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address
(A0, A1) could impose a transient wrong address. Therefore, this should be
done only while in the memory mode (E = CL = HIGH).
Serial-to-Parallel Capability
Output From Each Storage Bit Available
Random (Addressable) Data Entry
Easily Expandable
Active Low Common Clear
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC CL E Db Q3b Q2b Q1b Q0b
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
12
A0 A1
3 4 56 78
Da Q0a Q1a Q2a Q3a GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
A0, A1
Da, Db
E
Address Inputs
Data Inputs
Enable Input (Active LOW)
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
CL Clear Input (Active LOW)
0.5 U.L.
0.25 U.L.
Q0a – Q3a,
Q0b – Q3b
Parallel Latch Outputs (Note b)
10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
SN54/74LS256
DUAL 4-BIT
ADDRESSABLE LATCH
LOW POWER SCHOTTKY
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
3
2 1 15
14 13
Da E
A0
A1
CL
Q0a Q1a Q2a Q3a
A0 E Db
A1
CL
Q0b Q1b Q2b Q3b
4 56 7
9 10 11 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-1


74LS256 데이터시트, 핀배열, 회로
LOGIC DIAGRAM
E
14
Da
3
A0
1
SN54 / 74LS256
A1 CL Db
2 15 13
4
Q0a
5
Q1a
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
6
Q2a
CL E
LH
LL
LL
LL
LL
LL
LL
LL
LL
HH
HL
HL
HL
HL
HL
HL
HL
HL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
D
X
L
H
L
H
L
H
L
H
X
L
H
L
H
L
H
L
H
E
L
H
L
H
7
Q3a
9
Q0b
10
Q1b
TRUTH TABLE
A0 A1 Q0 Q1 Q2
XXL L L
LLLLL
L LHL L
HL L L L
HL LHL
LHL L L
LHL LH
HHL L L
HHL L L
X X QN–1 QN–1 QN–1
L L L QN–1 QN–1
L L H QN–1 QN–1
H L QN–1 L QN–1
H L QN–1 H QN–1
L H QN–1 QN–1 L
L H QN–1 QN–1 H
H H QN–1 QN–1 QN–1
H H QN–1 QN–1 QN–1
MODE SELECTION
CL MODE
H Addressable Latch
H Memory
L Dual 4-Channel Demultiplexer
L Clear
11
Q2b
12
Q3b
Q3
L
L
L
L
L
L
L
L
H
QN–1
QN–1
QN–1
QN–1
QN–1
QN–1
QN–1
L
H
MODE
Clear
Demultiplex
Memory
Addressable
Latch
FAST AND LS TTL DATA
5-2




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제조업체: Motorola Semiconductors

( motorola )

74LS256 latch

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