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PDF 74HC3GU04 Data sheet ( Hoja de datos )
| Número de pieza | 74HC3GU04 | |
| Descripción | Inverter | |
| Fabricantes | NXP Semiconductors | |
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74HC3GU04
Inverter
Rev. 03 — 11 May 2009
Product data sheet
1. General description
The 74HC3GU04 is a high-speed Si-gate CMOS device. This device provides three
inverter gates with unbuffered outputs.
The 74HC3GU04 has CMOS input switching levels and supply voltage range 2 V to 6 V.
2. Features
I Wide supply voltage range from 2.0 V to 6.0 V
I Symmetrical output impedance
I High noise immunity
I Low-power dissipation
I Balanced propagation delays
I Multiple package options
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC3GU04DP −40 °C to +125 °C TSSOP8
74HC3GU04DC −40 °C to +125 °C VSSOP8
74HC3GU04GD −40 °C to +125 °C XSON8U
Description
Version
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
4. Marking
Table 2. Marking
Type number
74HC3GU04DP
74HC3GU04DC
74HC3GU04GD
Marking code
HU04
HU4
HU4
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74HC3GU04
Inverter
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min Typ[1] Max
tt transition time nY; see Figure 5
[3]
VCC = 2.0 V
- 18 95
VCC = 4.5 V
- 6 19
VCC = 6.0 V
CPD power dissipation VI = GND to VCC
capacitance
-
[4] -
5 16
5-
−40 °C to +125 °C Unit
Min Max
- 125 ns
- 25 ns
- 20 ns
- - pF
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTLH and tTHL.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
VI
nA input
GND
VOH
nY output
VOL
VM
t PHL
VM
t THL
VM
VM
10 %
t PLH
90 %
t TLH
mna722
Measurement points are given in Table 9.
Fig 5. Propagation delay data input (nA) to data output (nY) and transition time output (nY)
Table 9. Measurement points
Type
74HC3GU04
Input
VM
0.5 × VCC
Output
VM
0.5 × VCC
74HC3GU04_3
Product data sheet
Rev. 03 — 11 May 2009
© NXP B.V. 2009. All rights reserved.
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74HC3GU04
Inverter
15. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
y
Z
8
5
c
E AX
HE v M A
pin 1 index
1
e
4
bp w M
A A2
A1
(A3)
detail X
Lp
L
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
D(1)
3.1
2.9
E(1) e
3.1
2.9
0.65
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
HE
4.1
3.9
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT505-2
---
L Lp v w y Z(1)
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
θ
8°
0°
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
Fig 15. Package outline SOT505-2 (TSSOP8)
74HC3GU04_3
Product data sheet
Rev. 03 — 11 May 2009
© NXP B.V. 2009. All rights reserved.
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