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NXP Semiconductors |
74LVC3G04
Triple inverter
Rev. 01 — 4 May 2004
Product data sheet
1. General description
The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC3G04 provides three inverting buffers.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant outputs for interfacing with 5 V logic
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V).
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s ±24 mA output drive (VCC = 3.0 V)
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s SOT505-2 and SOT765-1 package
s Specified from −40 °C to +85 °C and −40 °C to +125 °C.
Philips Semiconductors
74LVC3G04
Triple inverter
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; Tamb = 25 °C.
Symbol Parameter
tPHL, tPLH propagation delay
inputs nA to output nY
CI input capacitance
CPD power dissipation
capacitance
Conditions
Min
VCC = 1.8 V;
CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V;
CL = 30 pF; RL = 500 Ω
VCC = 2.7 V;
CL = 50 pF; RL = 500 Ω
VCC = 3.3 V;
CL = 50 pF; RL = 500 Ω
VCC = 5.0 V;
CL = 50 pF; RL = 500 Ω
-
-
-
-
-
-
VCC = 3.3 V
[1] [2] -
Typ Max Unit
3.5 -
ns
2.2 -
ns
2.7 -
ns
2.7 -
ns
1.9 -
ns
2.5 -
13.5 -
pF
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC.
4. Ordering information
Table 2: Ordering information
Type number Package
Temperature range Name
74LVC3G04DP −40 °C to +125 °C TSSOP8
74LVC3G04DC −40 °C to +125 °C VSSOP8
Description
Version
plastic thin shrink small outline package; 8 leads; body
width 3 mm; lead length 0.5 mm
SOT505-2
plastic very thin shrink small outline package; 8 leads; body SOT765-1
width 2.3 mm
9397 750 13075
Product data sheet
Rev. 01 — 4 May 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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