74LVC2GU04GM 반도체 회로 부품 판매점

Dual inverter



NXP Semiconductors 로고
NXP Semiconductors
74LVC2GU04GM 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
74LVC2GU04
Dual inverter
Product specification
Supersedes data of 2004 May 24
2004 Sep 21

74LVC2GU04GM 데이터시트, 핀배열, 회로
Philips Semiconductors
Dual inverter
Product specification
74LVC2GU04
FEATURES
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• ±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Multiple package options
Specified from 40 °C to +85 °C and 40 °C to +125 °C.
DESCRIPTION
The 74LVC2GU04 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Input can be driven from either 3.3 V or 5 V devices.
These features allow the use of these devices in a mixed
3.3 V and 5 V environment.
The 74LVC2GU04 provides two inverters. Each inverter is
a single stage with unbuffered output.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay input nA to output nY
CI input capacitance
CPD power dissipation capacitance per gate
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 5.0 V; CL = 50 pF; RL = 500
VCC = 3.3 V; notes 1 and 2
TYPICAL
2.3
1.8
2.6
2.3
1.7
5
7.8
UNIT
ns
ns
ns
ns
ns
pF
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
2004 Sep 21
2




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74LVC2GU04GM inverter

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