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74VHC02PW 반도체 회로 부품 판매점

Quad 2-input NOR gate



NXP Semiconductors 로고
NXP Semiconductors
74VHC02PW 데이터시트, 핀배열, 회로
74VHC02; 74VHCT02
Quad 2-input NOR gate
Rev. 01 — 13 August 2009
Product data sheet
1. General description
The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7-A.
The 74VHC02; 74VHCT02 provide a quad 2-input NOR function.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Inputs accept voltages higher than VCC
I Input levels:
N The 74VHC02 operates with CMOS input level
N The 74VHCT02 operates with TTL input level
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74VHC02D
40 °C to +125 °C SO14
74VHCT02D
74VHC02PW 40 °C to +125 °C TSSOP14
74VHCT02PW
74VHC02BQ
40 °C to +125 °C DHVQFN14
74VHCT02BQ
Description
plastic small outline package; 14 leads;
body width 3.9 mm
Version
SOT108-1
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm


74VHC02PW 데이터시트, 핀배열, 회로
NXP Semiconductors
4. Functional diagram
74VHC02; 74VHCT02
Quad 2-input NOR gate
2 1A
3 1B
5 2A
6 2B
8 3A
9 3B
11 4A
12 4B
1Y 1
2Y 4
3Y 10
4Y 13
mna216
Fig 1. Logic symbol
2
1
3
1
5
1
6
4
8
1
9
10
11
1
12
13
001aah084
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna215
Fig 3. Logic diagram (one gate)
1Y 1
1A 2
1B 3
2Y 4
2A 5
2B 6
GND 7
74VHC02
74VHCT02
14 VCC
13 4Y
12 4B
11 4A
10 3Y
9 3B
8 3A
001aak052
Fig 4. Pin configuration SO14 and TSSOP14
74VHC02
74VHCT02
terminal 1
index area
1A 2
1B 3
2Y 4
2A 5
2B 6
GND(1)
13 4Y
12 4B
11 4A
10 3Y
9 3B
001aak053
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration DHVQFN14
74VHC_VHCT02_1
Product data sheet
Rev. 01 — 13 August 2009
© NXP B.V. 2009. All rights reserved.
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74VHC02PW gate

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74VHC02PW

Quad 2-input NOR gate - NXP Semiconductors