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74ALVC32 반도체 회로 부품 판매점

Quad 2-input OR gate



NXP Semiconductors 로고
NXP Semiconductors
74ALVC32 데이터시트, 핀배열, 회로
74ALVC32
Quad 2-input OR gate
Rev. 3 — 20 January 2014
Product data sheet
1. General description
The 74ALVC32 is a quad 2-input OR gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
2. Features and benefits
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74ALVC32D 40 C to +85 C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74ALVC32PW 40 C to +85 C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74ALVC32BQ 40 C to +85 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1


74ALVC32 데이터시트, 핀배열, 회로
NXP Semiconductors
4. Functional diagram
74ALVC32
Quad 2-input OR gate
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Fig 1. Logic symbol
< 
< 
< 
< 
PQD

•


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 • 

PQD
Fig 2. IEC logic symbol
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Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
<
PQD
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
32 11 4Y
10 3B
9 3A
8 3Y
001aad101
Fig 4. Pin configuration SO14 and TSSOP14
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
32
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aad102
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DHVQFN14
74ALVC32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
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74ALVC32 gate

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