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PDF QL3004E Data sheet ( Hoja de datos )
| Número de pieza | QL3004E | |
| Descripción | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | |
| Fabricantes | QuickLogic Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de QL3004E (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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4,000 Usable PLD Gates with 82 I/Os
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400 MHz Datapaths
0.35 µm four-layer metal non-volatile CMOS
process for smallest die sizes
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100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
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Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
Two global clock/control networks available
to the logic cell; F1, clock, set and reset
inputs and the data input, I/O register clock,
reset and enable inputs as well as the output
enable control — each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
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Input + logic cell + output total delays
under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
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Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
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74 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
Four High-Drive input-only pins
Four High-Drive/distributed network pins
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Input Delay (bidirectional pad)
1.3 1.6 1.8 2.1 3.1 3.6
Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
Input Register Clock To Q
0.7 1.0 1.2 1.5 2.5 3.0
Input Register Reset Delay
0.6 0.9 1.1 1.4 2.4 2.9
Input Register clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3
Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0
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Output Delay Low to High
2.1 2.5 3.1
3.6
4.7
Output Delay High to Low
2.2 2.6 3.2
3.7
4.8
Output Delay Tri-state to High 1.2 1.7 2.2
2.8
3.9
Output Delay Tri-state to Low
1.6
2.0
2.6
Output Delay High to Tri-State a 2.0
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3.1
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Output Delay Low to Tri-State 1.2
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The 1149.1 standard requires the following three tests:
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• Extest Instruction. The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan register to
be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary
scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input
boundary cells capture the input data for analysis.
• Sample/Preload Instruction. This instruction allows a device to remain in its functional
mode, while selecting the boundary scan register to be connected between the TDI and TDO
pins. For this test, the boundary scan register can be accessed via a data scan operation,
allowing users to sample the functional data entering and leaving the device.
• Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan
entirely, so the data passes through the bypass register. The Bypass instruction allows users
to test a device without passing through other devices. The bypass register is connected
between the TDI and TDO pins, allowing serial data to be transferred through a device
without affecting the operation of the device.
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11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet QL3004E.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| QL3004 | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | QuickLogic Corporation |
| QL3004E | PLD Gate pASIC 3 FPGA Combining High Performance and High Density | QuickLogic Corporation |
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