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QL3060 반도체 회로 부품 판매점

PLD Gate pASIC 3 FPGA Combining High Performance and High Density



QuickLogic Corporation 로고
QuickLogic Corporation
QL3060 데이터시트, 핀배열, 회로
QL3060 pASIC 3 FPGA Data Sheet
• • • • • • 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
Device Highlights
High Performance & High Density
60,000 Usable PLD Gates with 316 I/Os
www.DataS3h0ee0t4MU.cHozm16-bit Counters,
400 MHz Datapaths
0.35 µm four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
Eight Low-Skew Distributed
Networks
Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
Six global clock/control networks available
to the logic cell F1, clock set, and reset
inputs and the input and I/O register clock,
reset, and enable inputs as well as the output
enable control — each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
High Performance
Input + logic cell + output total delays
under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
Advanced I/O Capabilities
Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 316 I/O Pins
308 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
Eight high-drive input/distributed
network pins
Figure 1: 1,584 pASIC 3 Logic Cells
© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3060 데이터시트, 핀배열, 회로
QL3060 pASIC 3 FPGA Data Sheet Rev D
Architecture Overview
The QL3060 is a 60,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC
3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogic's patented
ViaLinktechnology to provide a unique combination of high performance, high density,
low cost, and extreme ease-of-use.
The QL3060 contains 1,584 logic cells. With a maximum of 316 I/Os, the QL3060 is
available in 208-PQFP and 456-pin PBGA packages.
Software support for the complete pASIC 3 family, including the QL3060, is available
through three basic packages. The turnkey QuickWorkspackage provides the most
complete FPGA software solution from design entry to logic synthesis, to place and route,
to simulation. The QuickToolsTM for Workstations package provides a solution for designers
who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM,
www.DataSheet4U.com or other third-party tools for design entry, synthesis, or simulation.
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www.quicklogic.com
© 2002 QuickLogic Corporation




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PLD Gate pASIC 3 FPGA Combining High Performance and High Density - QuickLogic Corporation