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KK74AC132 반도체 회로 부품 판매점

Quad 2-Input NAND Gate



KODENSHI KOREA 로고
KODENSHI KOREA
KK74AC132 데이터시트, 핀배열, 회로
TECHNICAL DATA
www.DataSheet4U.com
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
High-Performance Silicon-Gate CMOS
KK74AC132
The KK74AC132 is identical in pinout to the LS/ALS132, HC/HCT132.
The device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALS outputs.
The KK74AC132 can be used to enhance noise immunity or to square up
slowly changing waveforms.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74AC132N Plastic
KK74AC132D SOIC
TA = -40° to 85° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
AB
LL
LH
HL
HH
Output
Y
H
H
H
L
1


KK74AC132 데이터시트, 핀배열, 회로
KK74AC132
www.DataSheet4U.com
MAXIMUM RATINGS*
Symbol
Parameter
Value
VCC
VIN
VOUT
IIN
IOUT
ICC
PD
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
-0.5 to +7.0
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±20
±50
±50
750
500
Tstg Storage Temperature
-65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mA
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TJ Junction Temperature (PDIP)
TA Operating Temperature, All Package Types
IOH Output Current - High
IOL Output Current - Low
tr, tf Input Rise and Fall Time *
(except Schmitt Inputs)
* VIN from 30% to 70% VCC
VCC =3.0 V
VCC =4.5 V
VCC =5.5 V
Min Max Unit
2.0 6.0
V
0 VCC V
140 °C
-40 +85 °C
-24 mA
24 mA
0 150 ns/V
0 40
0 25
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or
VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2




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KK74AC132 gate

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