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74AUP1G04 반도체 회로 부품 판매점

Low power single inverter gate



STMicroelectronics 로고
STMicroelectronics
74AUP1G04 데이터시트, 핀배열, 회로
www.DataSheet4U.com
74AUP1G04
Low power single inverter gate
Features
High speed: tPD = 4.3 ns (max.) at VCC = 2.3 V
Power down protection on inputs and outputs
Balanced propagation delays:
tPLH tPHL
Operating voltage range:
VCC (opr) = 1.2 to 3.6 V
Low power dissipation:
ICC = 1 µA (max.) at TA = 85 °C
Latch-up performance exceeds 300 mA (JESD
78, Class II)
ESD performance:
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Applications
Mobile phones
Personal digital assistants (PDAs)
DFN6L
SOT-665
Description
The 74AUP1G04 is a low voltage CMOS single
inverter gate fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for 1.2 to 3.6 V operations
and low power and low noise applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
Table 1. Device summary
Order code
74AUPG04DTR
74AUPG04GTR
March 2008
Package
DFN6L (1.2 x 1 mm)
SOT-665 (1.6 x 1.6 mm)
Rev 1
Packing
Tape and reel
Tape and reel
1/18
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74AUP1G04 데이터시트, 핀배열, 회로
www.DataSPhienets4Ue.tctoinmgs
1 Pin settings
1.1 Pin connection
Figure 1. Pin connection (top through view)
74AUP1G04
1.2
NC 1
A2
GND 3
6 VCC
5 NC
4B
DFN6L
NC 1
A2
GND 3
5 VCC
4B
SOT-665
CS00092
Pin description
Table 2. Pin assignment
DFN pin
number
SOT pin
number
Symbol
1 1 NC
22A
3 3 GND
44B
5 - NC
6 5 VCC
Name and function
Not connected
Data input
Ground (0V)
Data output
Not connected
Positive supply voltage
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74AUP1G04 gate

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