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SY100E101 반도체 회로 부품 판매점

QUAD 4-INPUT OR/NOR GATE



Micrel Semiconductor 로고
Micrel Semiconductor
SY100E101 데이터시트, 핀배열, 회로
QUAD 4-INPUT
OR/NOR GATE
SY10E101
SY100E101
FEATURES
s 500ps max. propagation delay
s Extended 100E VEE range of –4.2V to –5.5V
s True and complementary outputs
s Fully compatible with industry standard 10KH,
100K I/O levels
s Internal 75Kinput pulldown resistors
s Fully compatible with Motorola MC10E/100E101
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E101 are quad 4-input OR/NOR gates
designed for use in new, high-performance ECL systems.
The E101 features both true and complementary outputs.
BLOCK DIAGRAM
D0a
D0b
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
D3a
D3b
D3c
D3d
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
PIN CONFIGURATION
D2d
D2c
D2b
VEE
D2a
D1d
D1c
25 24 23 22 21 20 19
26 18
27 17
28
PLCC
16
1
TOP VIEW
15
2
J28-1
14
3 13
4 12
5 6 7 8 9 10 11
Q2
Q2
VCC
Q1
Q1
Q0
Q0
PIN NAMES
Pin
Dna, Dnb, Dnc, Dnd
Q0-Q3
Q0-Q3
VCCO
Function
Data Inputs
True Outputs
Inverting Outputs
VCC to Output
Rev.: D Amendment: /2
1 Issue Date: May, 1998


SY100E101 데이터시트, 핀배열, 회로
Micrel
LOGIC EQUATION
Qn = Dna + Dnb + Dnc + Dnd
SY10E101
SY100E101
DC ELECTRICAL CHARACTERISTICS
VEE = VEE(Min.) to VEE(Max.); VCC = VCCO = GND
TA = –40°C
Symbol
Parameter
Min. Typ. Max.
IIH Input HIGH Current — — 150
IEE Power Supply Current
10EL — 30 36
100EL — 30 36
TA = 0°C
Min. Typ. Max.
— — 150
— 30 36
— 30 36
TA = +25°C
Min. Typ. Max.
— — 150
— 30 36
— 30 36
TA = +85°C
Min. Typ. Max.
— — 150
— 30 36
— 35 42
Unit
µA
mA
AC ELECTRICAL CHARACTERISTICS
VEE = VEE(Min.) to VEE(Max.); VCC = VCCO = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
tPLH
tPHL
Propagation Delay to
Output D to Q
150 — 550 200 350 500 200 350 500 200 350 500 ps
tskew
Within-Device Skew(1)
Within-Gate Skew(2)
— 50 —
— 25 —
— 50 —
— 25 —
— 50 —
— 25 —
— 50 — ps
— 25 — ps
tr Rise/Fall Time
tf 20% to 80%
275 — 625 300 380 575 300 380 575 300 380 575 ps
NOTES:
1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Within-gate skew is defined as the variation in propagation delays through a single gate when driven from its different inputs.
PRODUCT ORDERING CODE
Ordering
Code
SY10E101JC
SY10E101JCTR
SY100E101JC
SY100E101JCTR
Package
Type
J28-1
J28-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
Ordering
Code
SY10E101JI
SY10E101JITR
SY100E101JI
SY100E101JITR
Package
Type
J28-1
J28-1
J28-1
J28-1
Operating
Range
Industrial
Industrial
Industrial
Industrial
2




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SY100E101 gate

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