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PDF 74VHCT02 Data sheet ( Hoja de datos )
| Número de pieza | 74VHCT02 | |
| Descripción | QUAD 2-INPUT NOR GATE | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74VHCT02 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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® 74VHCT02A
QUAD 2-INPUT NOR GATE
s HIGH SPEED: tPD = 3.5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 02
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.8V (Max.)
DESCRIPTION
The 74VHCT02A is an advanced high-speed
CMOS QUAD 2-INPUT NOR GATE fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology.
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHCT02AM
74VHCT02AT
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 1999
1/7
1 page  
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
G
L
M
S
MIN.
0.1
0.35
0.19
8.55
5.8
3.8
4.6
0.5
SO-14 MECHANICAL DATA
mm
TYP.
0.5
1.27
7.62
MAX.
1.75
0.2
1.65
0.46
0.25
MIN.
0.003
0.013
0.007
45 (typ.)
8.75 0.336
6.2 0.228
4.0 0.149
5.3 0.181
1.27 0.019
0.68
8 (max.)
74VHCT02A
inch
TYP.
0.019
0.050
0.300
MAX.
0.068
0.007
0.064
0.018
0.010
0.344
0.244
0.157
0.208
0.050
0.026
P013G
5/7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74VHCT02.PDF ] | |
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