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PDF 74VHC32 Data sheet ( Hoja de datos )
| Número de pieza | 74VHC32 | |
| Descripción | QUAD 2-INPUT OR GATE | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74VHC32
s HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 32
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.8V (Max.)
DESCRIPTION
The 74VHC32 is an advanced high-speed CMOS
QUAD 2-INPUT OR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
QUAD 2-INPUT OR GATE
PRELIMINARY DATA
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC32M
74VHC32T
The internal circuit is composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/7
1 page  
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
G
L
M
S
MIN.
0.1
0.35
0.19
8.55
5.8
3.8
4.6
0.5
SO-14 MECHANICAL DATA
mm
TYP.
0.5
1.27
7.62
MAX.
1.75
0.2
1.65
0.46
0.25
MIN.
0.003
0.013
0.007
45 (typ.)
8.75 0.336
6.2 0.228
4.0 0.149
5.3 0.181
1.27 0.019
0.68
8 (max.)
inch
TYP.
0.019
0.050
0.300
74VHC32
MAX.
0.068
0.007
0.064
0.018
0.010
0.344
0.244
0.157
0.208
0.050
0.026
P013G
5/7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74VHC32.PDF ] | |
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