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NXP Semiconductors |
74LVC1G11
Single 3-input AND gate
Rev. 8 — 17 September 2015
Product data sheet
1. General description
The 74LVC1G11 provides a single 3-input AND gate.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall time.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
24 mA output drive (VCC = 3.0 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
NXP Semiconductors
74LVC1G11
Single 3-input AND gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC1G11GW
40 C to +125 C SC-88
74LVC1G11GV
40 C to +125 C SC-74
74LVC1G11GM
40 C to +125 C XSON6
74LVC1G11GF
40 C to +125 C XSON6
74LVC1G11GN
40 C to +125 C XSON6
74LVC1G11GS
40 C to +125 C XSON6
74LVC1G11GX
40 C to +125 C X2SON6
Description
Version
plastic surface-mounted package; 6 leads
SOT363
plastic surface-mounted package (TSOP6); 6 leads SOT457
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1.45 0.5 mm
SOT886
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1 0.5 mm
SOT891
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
plastic thermal extremely thin small outline package; SOT1255
no leads; 6 terminals; body 1 0.8 0.35 mm
4. Marking
Table 2. Marking
Type number
74LVC1G11GW
74LVC1G11GV
74LVC1G11GM
74LVC1G11GF
74LVC1G11GN
74LVC1G11GS
74LVC1G11GX
Marking code[1]
VU
V11
VU
VU
VU
VU
VU
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
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Fig 1. Logic symbol
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Fig 2. IEC logic symbol
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Fig 3. Logic diagram
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74LVC1G11
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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