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MC14011 반도체 회로 부품 판매점

B-Suffix Series CMOS Gates



ON Semiconductor 로고
ON Semiconductor
MC14011 데이터시트, 핀배열, 회로
MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
Pin–for–Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 2.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–14
P SUFFIX
CASE 646
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
MARKING
DIAGRAMS
14
MC140XXBCP
AWLYYWW
1
14
140XXB
AWLYWW
1
14
14
0XXB
ALYW
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC140XXB
AWLYWW
1
XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
DEVICE INFORMATION
Device
Description
MC14001B Quad 2–Input NOR Gate
MC14011B
Quad 2–Input NAND Gate
MC14023B Triple 3–Input NAND Gate
MC14025B Triple 3–Input NOR Gate
MC14071B Quad 2–Input OR Gate
MC14073B Triple 3–Input AND Gate
MC14081B
MC14082B
Quad 2–Input AND Gate
Dual 4–Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 1
1
Publication Order Number:
MC14001B/D


MC14011 데이터시트, 핀배열, 회로
NOR
MC14001B
Quad 2–Input NOR Gate
MC14001B Series
LOGIC DIAGRAMS
NAND
OR
MC14011B
Quad 2–Input NAND Gate
MC14071B
Quad 2–Input OR Gate
AND
MC14081B
Quad 2–Input AND Gate
1111
3333
2222
5555
4444
6666
8888
9 10 9 10 9 10 9 10
12 12 12 12
11 11 11 11
13 13 13 13
MC14025B
Triple 3–Input NOR Gate
MC14023B
MC14073B
Triple 3–Input NAND Gate Triple 3–Input AND Gate
MC14082B
Dual 4–Input AND Gate
1
29
8
3
46
5
11
12 10
13
MC14001B
Quad 2–Input NOR Gate
1
2
8
1
92
8
2
93
4
1
335
4 64 69
5
11
5
11
10
11
13
12 10 12 10 12
13 13
NC = 6, 8
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
PIN ASSIGNMENTS
MC14011B
Quad 2–Input NAND Gate
MC14023B
Triple 3–Input NAND Gate
MC14025B
Triple 3–Input NOR Gate
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
IN 1A
IN 2A
IN 1B
IN 2B
IN 3B
OUTB
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 3C
12 IN 2C
11 IN 1C
10 OUTC
9 OUTA
8 IN 3A
IN 1A
IN 2A
IN 1B
IN 2B
IN 3B
OUTB
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 3C
12 IN 2C
11 IN 1C
10 OUTC
9 OUTA
8 IN 3A
MC14071B
Quad 2–Input OR Gate
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
MC14073B
Triple 3–Input AND Gate
IN 1A
IN 2A
IN 1B
IN 2B
IN 3B
OUTB
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 3C
12 IN 2C
11 IN 1C
10 OUTC
9 OUTA
8 IN 3A
MC14081B
Quad 2–Input AND Gate
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
http://onsemi.com
2
MC14082B
Dual 4–Input AND Gate
OUTA
IN 1A
IN 2A
IN 3A
IN 4A
NC
VSS
1
2
3
4
5
6
7
14 VDD
13 OUTB
12 IN 4B
11 IN 3B
10 IN 2B
9 IN 1B
8 NC
NC = NO CONNECTION




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