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MC14002UBCL 반도체 회로 부품 판매점

UB-Suffix Series COMS Gates



Motorola Semiconductors 로고
Motorola Semiconductors
MC14002UBCL 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
UB-Suffix Series CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
non–buffered functions.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linear and Oscillator Applications
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
Devices
LOGIC DIAGRAMS
MC14001UB
Quad 2–Input
NOR Gate
1
23
54
6
8
10
9
12
11
13
MC14012UB
Dual 4–Input
NAND Gate
2
3
1
4
5
9
10 13
11
12
NC = 6, 8
MC14002UB
Dual 4–Input
NOR Gate
2
3
41
5
9
10
13
11
12 NC = 6, 8
MC14011UB
Quad 2–Input
NAND Gate
1
3
2
5
4
6
8
10
9
12
11
13
MC14023UB
Triple 3–Input
NAND Gate
1
29
8
3
46
5
11
12 10
13
MC14025UB
Triple 3–Input
NOR Gate
1
2
8
3
4
5
11
12
13
9
6
10
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
MC14001UB
Quad 2-Input NOR Gate
MC14002UB
Dual 4-Input NOR Gate
MC14011UB
Quad 2-Input NAND Gate
MC14012UB
Dual 4-Input NAND Gate
MC14023UB
Triple 3-Input NAND Gate
MC14025UB
Triple 3-Input NOR Gate
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v voperation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
REV 3
1/94
©MMCot1or4o0la0, I1nUc.B1995
18
MOTOROLA CMOS LOGIC DATA


MC14002UBCL 데이터시트, 핀배열, 회로
MC14001UB
Quad 2–Input NOR Gate
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
PIN ASSIGNMENTS
MC14002UB
Dual 4–Input NOR Gate
OUTA
IN 1A
IN 2A
IN 3A
IN 4A
NC
VSS
1
2
3
4
5
6
7
14 VDD
13 OUTB
12 IN 4B
11 IN 3B
10 IN 2B
9 IN 1B
8 NC
MC14012UB
Dual 4–Input NAND Gate
MC14023UB
Triple 3–Input NAND Gate
OUTA
IN 1A
IN 2A
IN 3A
IN 4A
NC
VSS
1
2
3
4
5
6
7
14 VDD
13 OUTB
12 IN 4B
11 IN 3B
10 IN 2B
9 IN 1B
8 NC
IN 1A
IN 2A
IN 1B
IN 2B
IN 3B
OUTB
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 3C
12 IN 2C
11 IN 1C
10 OUTC
9 OUTA
8 IN 3A
NC = NO CONNECTION
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (VoltagesReferenced to VSS)
Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD DC Supply Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout Input or Output Voltage (DC or Transient)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎlin, lout Input or Output Current (DC or Transient),
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎper Pin
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
± 10
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature(8–SecondSoldering)
500
– 65 to + 150
260
mW
_C
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MC14011UB
Quad 2–Input NAND Gate
IN 1A
IN 2A
OUTA
OUTB
IN 1B
IN 2B
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
MC14025UB
Triple 3–Input NOR Gate
IN 1A
IN 2A
IN 1B
IN 2B
IN 3B
OUTB
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 3C
12 IN 2C
11 IN 1C
10 OUTC
9 OUTA
8 IN 3A
MOTOROLA CMOS LOGIC DATA
MC14001UB
19




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MC14002UBCL gate

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