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System Logic Semiconductor |
Quad 2-Input OR Gate
SL74HCT32
High-Performance Silicon-Gate CMOS
The SL74HCT32 may be used as a level converter for interfacing
TTL or NMOS outputs to High-Speed CMOS inputs.
The SL74HCT32 is identical in pinout to the LS/ALS32.
• TTL/NMOS-Compatible Input Levels.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
SL74HCT32N Plastic
SL74HCT32D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
SLS
System Logic
Semiconductor
FUNCTION TABLE
Inputs
AB
LL
LH
HL
HH
Output
Y
L
H
H
H
SL74HCT32
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
IIN
IOUT
ICC
PD
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
±25
±50
750
500
Tstg Storage Temperature
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
-65 to +150
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mA
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
TA
tr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
Min Max Unit
4.5 5.5
V
0 VCC
-55 +125
V
°C
0 500 ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor
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