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PDF 74AC11B Data sheet ( Hoja de datos )
| Número de pieza | 74AC11B | |
| Descripción | TRIPLE 3-INPUT AND GATE | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74AC11B (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
D Independent Registers and Enables for A
and B Buses
DW PACKAGE
(TOP VIEW)
D Multiplexed Real-Time and Stored Data
D Inverting Data Paths
D Flow-Through Architecture Optimizes PCB
OEAB
A1
A2
1
2
3
28 CLKAB
27 SAB
26 B1
Layout
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
A3
A4
GND
4
5
6
25 B2
24 B3
23 B4
D EPIC ™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
GND
GND
GND
A5
A6
7
8
9
10
11
22 VCC
21 VCC
20 B5
19 B6
18 B7
description
A7 12
A8 13
17 B8
16 CLKBA
The 74AC11652 consists of bus transceiver
OEBA 14 15 SBA
circuits, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions.
The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred.
A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four
fundamental bus-management functions that can be performed with the 74AC11652.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when
all other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
The 74AC11652 is characterized for operation from – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
1 page  
recommended operating conditions
VCC Supply voltage
VIH High-level input voltage
VIL Low-level input voltage
VI Input voltage
VO Output voltage
IOH High-level output current
IOL Low-level output current
∆t /∆v
TA
Input transition rise or fall rate
Operating free-air temperature
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
Control pins
Data
MIN NOM MAX UNIT
3 5 5.5 V
2.1
3.15 V
3.85
0.9
1.35 V
1.65
0 VCC V
0 VCC V
–4
– 24 mA
– 24
12
24 mA
24
05
ns/ V
0 10
– 40 85 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN TYP MAX
3 V 2.9
IOH = – 50 µA
4.5 V
5.5 V
4.4
5.4
VOH
IOH = – 4 mA
IOH = – 24 mA
IOH = – 75 mA†
3V
4.5 V
5.5 V
5.5 V
3V
2.58
3.94
4.94
0.1
IOL = 50 µA
4.5 V
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V 0.36
IOL = 24 mA
4.5 V
5.5 V
0.36
0.36
IOL = 75 mA†
5.5 V
II Control inputs VI = VCC or GND
IOZ‡ A or B ports VO = VCC or GND
5.5 V
5.5 V
± 0.1
± 0.5
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
Ci Control inputs VI = VCC or GND
5 V 4.5
Cio A or B ports VO = VCC or GND
5 V 12
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
MIN MAX UNIT
2.9
4.4
5.4
2.48
3.8
4.8
3.85
0.1
0.1
0.1
0.44
0.44
0.44
1.65
±1
±5
80
V
V
µA
µA
µA
pF
pF
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74AC11B.PDF ] | |
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