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NXP Semiconductors |
INTEGRATED CIRCUITS
DATA SHEET
74AUC1G08
Single 2-input AND gate
Preliminary specification
File under Integrated Circuits, IC24
2002 Nov 12
Philips Semiconductors
Single 2-input AND gate
Preliminary specification
74AUC1G08
FEATURES
• Wide supply voltage range from 0.8 to 2.7 V
• Performance optimised for VCC = 1.8 V
• High noise immunity
• Complies with JEDEC standard:
– JESD76 (1.65 to 1.95 V)
• ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
• 8 mA output drive (VCC = 1.65 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• 3.3 V tolerant inputs/outputs
• SC-88A and SC-74A package.
DESCRIPTION
The 74AUC1G08 is a high-performance, low-power,
low-voltage, Si-gate CMOS device.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall time.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging current backflow through the
device when it is powered down.
The 74AUC1G08 provides the single 2-input AND
function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; input slewrate ≥ 1 V/ns.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay inputs A and B to
output Y
CI input capacitance
CPD power dissipation capacitance per buffer
CONDITIONS
VCC = 0.8 V; CL = 15 pF; RL = 2 kΩ
VCC = 1.2 V; CL = 15 pF; RL = 2 kΩ
VCC = 1.5 V; CL = 15 pF; RL = 2 kΩ
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
VCC = 1.8 V; notes 1 and 2
TYPICAL UNIT
4.7 ns
1.9 ns
1.4 ns
1.4 ns
1.2 ns
4 pF
14 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
2002 Nov 12
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