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Fairchild Semiconductor |
August 1990
Revised August 2000
74ACTQ10
Quiet Series Triple 3-Input NAND Gate
General Description
The ACTQ10 contains three, 3-input NAND gates and uti-
lizes Fairchild FACT Quiet Series technology to guaran-
tee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series features GTO output
control and undershoot corrector in addition to a split
ground bus for superior ACMOS performance.
Features
s ICC reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Improved latch-up immunity
s Outputs source/sink 24 mA
s ACTQ 10 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ10SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACTQ10MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ10PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
An, Bn, Cn
On
Descriptions
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010892
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
DC Latch-Up Source or Sink Current
Junction Temperature (TJ)
PDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
± 50 mA
± 50 mA
−65°C to +150°C
± 300 mA
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
4.5V to 5.5V
0V to VCC
0V to VCC
−40°C to +85°C
125 mV/ns
Note 1: Absolute maximum ratings are values beyond which damage to the
device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power sup-
ply, temperature, and output/input loading variables. Fairchild does not rec-
ommend operation outside of databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C Units
(V) Typ
Guaranteed Limits
Conditions
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
4.5 1.5
5.5 1.5
4.5 1.5
5.5 1.5
4.5 4.49
5.5 5.49
2.0
2.0
0.8
0.8
4.4
5.4
2.0 V VOUT = 0.1V
2.0 or VCC − 0.1V
0.8 V VOUT = 0.1V
0.8 or VCC − 0.1V
4.4
5.4 V IOUT = −50 µA
VOL Maximum LOW Level
Output Voltage
4.5
5.5
4.5 0.001
5.5 0.001
3.86
4.86
0.1
0.1
3.76
4.76
0.1
0.1
VIN = VILor VIH
V IOH = − 24 mA
IOH = − 24 mA (Note 2)
V IOUT = 50 µA
4.5
5.5
IIN Maximum Input Leakage Current
5.5
ICCT
Maximum ICC/Input
5.5 0.6
IOLD
Minimum Dynamic
5.5
IOHD
Output Current (Note 3)
5.5
ICC Maximum Quiescent Supply Current
5.5
VOLP
Quiet Output
Maximum Dynamic VOL
5.0 1.1
VOLV
Quiet Output
Minimum Dynamic VOL
5.0 −0.6
VIHD
Minimum HIGH Level Dynamic Input Voltage 5.0
1.9
VILD Maximum LOW Level Dynamic Input Voltage 5.0
1.2
Note 2: All outputs loaded; thresholds on input associated with output under test.
0.36
0.36
± 0.1
2.0
1.5
−1.2
2.2
0.8
0.44
0.44
± 1.0
1.5
75
−75
20.0
VIN = VILor VIH
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
mA VI = VCC − 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC or GND
Figures 1, 2
V
(Note 4)(Note 5)
Figures 1, 2
V
(Note 4)(Note 5)
V (Note 4)(Note 6)
V (Note 4)(Note 6)
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP Package.
Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n-1) inputs switching 0V to 3V. Input-under-test switching:
3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHZ.
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