74LVC2G00-Q100 반도체 회로 부품 판매점

Dual 2-input NAND gate



NXP Semiconductors 로고
NXP Semiconductors
74LVC2G00-Q100 데이터시트, 핀배열, 회로
74LVC2G00-Q100
Dual 2-input NAND gate
Rev. 1 — 3 September 2015
Product data sheet
1. General description
The 74LVC2G00-Q100 provides a 2-input NAND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

74LVC2G00-Q100 데이터시트, 핀배열, 회로
NXP Semiconductors
74LVC2G00-Q100
Dual 2-input NAND gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC2G00DC-Q100 40 C to +125 C VSSOP8
Description
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
Version
SOT765-1
4. Marking
Table 2. Marking codes
Type number
74LVC2G00DC-Q100
Marking code[1]
V00
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
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DDK
Fig 1. Logic symbol
DDK
Fig 2. IEC logic symbol
6. Pinning information
6.1 Pinning
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PQD
Fig 3. Logic diagram (one gate)
Fig 4. Pin configuration SOT765-1
/9&*4
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DDD
74LVC2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74LVC2G00-Q100 gate

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74LVC2G00-Q100

Dual 2-input NAND gate - NXP Semiconductors