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Número de pieza | 74ALVCH16374 | |
Descripción | Low-Voltage 16-Bit D-Type Flip-Flop | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! 74ALVCH16374
Low−Voltage 16−Bit D−Type
Flip−Flop with Bus Hold
1.8/2.5/3.3 V
(3−State, Non−Inverting)
The 74ALVCH16374 is an advanced performance, non−inverting
16−bit D−type flip−flop. It is designed for very high−speed, very
low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCXH16374 is byte controlled, with each byte functioning
identically, but independently. Each byte has separate Output Enable
and Clock Pulse inputs. These control pins can be tied together for full
16−bit operation.
The 74ALVCH16374 consists of 16 edge−triggered flip−flops with
individual D−type inputs and 3.6 V−tolerant 3−state outputs. The
clocks (CPn) and Output Enables (OEn) are common to all flip−flops
within the respective byte. The flip−flops will store the state of
individual D inputs that meet the setup and hold time requirements on
the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the
contents of the flip−flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. The OE input level
does not affect the operation of the flip−flops. The data inputs include
active bushold circuitry, eliminating the need for external pull−up
resistors to hold unused or floating inputs at a valid logic state.
• Designed for Low Voltage Operation: VCC = 1.65 − 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.6 ns max for 3.0 to 3.6 V
4.5 ns max for 2.3 to 2.7 V
7.8 ns max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
• IOFF Specification Guarantees High Impedance When VCC = 0 V†
• Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• Second Source to Industry Standard 74ALVCH16374
http://onsemi.com
MARKING DIAGRAM
48
48
1
TSSOP−48
DT SUFFIX
CASE 1201
74ALVCH16374DT
AWLYYWW
1
A = Assembly
Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN NAMES
Pins
Function
OEn
CPn
D0−D15
O0−O15
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
ORDERING INFORMATION
Device
Package
74ALVCH16374DTR
TSSOP
Shipping
2500 / Reel
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to VCC through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 3
1
Publication Order Number:
74ALVCH16374/D
1 page 74ALVCH16374
AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
Limits
TA = −40°C to +85°C
Symbol
Parameter
Wave− VCC = 3.0 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V
form
Min
Max
Min
Max
Min
Max
Unit
fmax Clock Pulse Frequency
1 250
200
100
MHz
tPLH Propagation Delay
tPHL
CP to On
1 1.0 3.6 1.0 4.5 1.0
1.0 3.6 1.0 4.5 1.0
7.8 ns
7.8
tPZH
tPZL
Output Enable Time to
High and Low Level
2 1.0 4.7 1.0 6.0 1.0
1.0 4.7 1.0 6.0 1.0
9.2 ns
9.2
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2 1.0 4.1 1.0 5.1 1.5
1.0 4.1 1.0 5.1 1.5
6.8 ns
6.8
ts
Setup Time, High or Low Dn to CP
3
1.5
0.5
2.5
ns
th
Hold Time, High or Low Dn to CP
3
1.0
0.5
1.0
ns
tw CP Pulse Width, High
3 1.5
0.5
4.0
ns
tOSHL Output−to−Output Skew
0.5 0.5
0.75 ns
tOSLH
(Note 11)
0.5 0.5
0.75
10. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
CPD Power Dissipation Capacitance
12. VCC = 1.8, 2.5 or 3.3 V; VI = 0 V or VCC.
Condition
Note 12
Note 12
Note 12, 10 MHz
Typical
6
7
20
Unit
pF
pF
pF
Dn
ts
CPn
On
Vm
th
Vm
fmax
tPLH, tPHL
Vm
VIH
Vm
0V
VIH
Vm
0V
VOH
OEn
tPZH
On
tPZL
On
VOL
Vm
tPHZ
Vm
tPLZ
Vm
Vm
VIH
0V
VOH
Vy
≈0V
≈ VCC
Vx
VOL
WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 4. AC Waveforms
http://onsemi.com
5
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet 74ALVCH16374.PDF ] |
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