74ALVC16374 반도체 회로 부품 판매점

Low-Voltage 1.8/2.5/3.3V 16-Bit D-Type Flip-Flop



ON Semiconductor 로고
ON Semiconductor
74ALVC16374 데이터시트, 핀배열, 회로
74ALVC16374
Low−Voltage 1.8/2.5/3.3 V
16−Bit D−Type Flip−Flop
With 3.6 VTolerant Inputs and Outputs
(3State, NonInverting)
The 74ALVC16374 is an advanced performance, noninverting
16bit Dtype flipflop. It is designed for very highspeed, very
lowpower operation in 1.8 V, 2.5 V or 3.3 V systems. The
ALVC16374 is byte controlled, with each byte functioning identically,
but independently. Each byte has separate Output Enable and Clock
Pulse inputs. These control pins can be tied together for a full 16bit
operation.
The 74ALVC16374 consists of 16 edgetriggered flipflops with
individual Dtype inputs and 3.6 Vtolerant 3state outputs. The
clocks (CPn) and Output Enables (OEn) are common to all flipflops
within the respective byte. The flipflops will store the state of
individual D inputs that meet the setup and hold time requirements on
the LOWtoHIGH Clock (CP) transition. With the OE LOW, the
contents of the flipflops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. The OE input level
does not affect the operation of the flipflops.
Designed for Low Voltage Operation: VCC = 1.653.6 V
3.6 V Tolerant Inputs and Outputs
High Speed Operation: 3.6 ns max for 3.0 to 3.6 V
4.5 ns max for 2.3 to 2.7 V
7.8 ns max for 1.65 to 1.95 V
Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds ±250 mA @ 125°C
ESD Performance: Human Body Model >2000 V; Machine Model
>200 V
Second Source to Industry Standard 74ALVC16374
†To ensure the outputs activate in the 3state condition, the output enable pins
should be connected to VCC through a pullup resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
http://onsemi.com
MARKING DIAGRAM
48
48
1
TSSOP48
DT SUFFIX
CASE 1201
74ALVC16374DT
AWLYYWW
1
A = Assembly
Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN NAMES
Pins
Function
OEn
CPn
D0D15
O0O15
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
ORDERING INFORMATION
Device
Package
Shipping
74ALVC16374DTR TSSOP 2500/Tape & Reel
© Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 1
1
Publication Order Number:
74ALVC16374/D

74ALVC16374 데이터시트, 핀배열, 회로
74ALVC16374
OE1 1
O0 2
O1 3
GND 4
O2 5
O3 6
VCC 7
O4 8
O5 9
GND 10
O6 11
O7 12
O8 13
O9 14
GND 15
O10 16
O11 17
VCC 18
O12 19
O13 20
GND 21
O14 22
O15 23
OE2 24
48 CP1
47 D0
46 D1
45 GND
44 D2
43 D3
42 VCC
41 D4
40 D5
39 GND
38 D6
37 D7
36 D8
35 D9
34 GND
33 D10
32 D11
31 VCC
30 D12
29 D13
28 GND
27 D14
26 D15
25 CP2
Figure 1. 48Lead Pinout
(Top View)
1
OE1
48
CP1
47
D0
nCP
Q
D
2
O0
24
OE2
25
CP2
36
D8
nCP
Q
D
46
D1
nCP
Q
D
3
O1
35
D9
nCP
Q
D
44
D2
nCP
Q
D
5
O2
33
D10
nCP
Q
D
43
D3
nCP
Q
D
6
O3
32
D11
nCP
Q
D
41
D4
nCP
Q
D
8
O4
30
D12
nCP
Q
D
40
D5
nCP
Q
D
9
O5
29
D13
nCP
Q
D
38
D6
nCP
Q
D
11
O6
27
D14
nCP
Q
D
37
D7
nCP
Q
D
12
O7
26
D15
nCP
D
Figure 2. Logic Diagram
Q
1
OE1
CP1
48
25
CP2 24
OE2
EN1
EN2
EN3
EN4
D0 47
D1 46
D2 44
D3
D4
43
41
D5 40
D6 38
D7
D8
37
36
D9 35
D10 33
D11
D12
32
30
D13 29
D14 27
D15 26
1 1
1 2
1 3
1 4
2 O0
3 O1
5 O2
6
8
O3
O4
9 O5
11 O6
12
13
O7
O8
14 O9
16 O10
17
19
O11
O12
20 O13
22 O14
23 O15
Figure 3. IEC Logic Diagram
13
O8
14
O9
16
O10
17
O11
19
O12
20
O13
22
O14
23
O15
Inputs
Outputs
Inputs
Outputs
CP1 OE1 D0:7
O0:7
CP2
OE2
D8:15
O8:15
LH H LH H
L L L L L L
X L X O0 X L X O0
X H X Z XH X Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; = LowtoHigh Transition; X = High or Low Voltage Level and
Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputs. O0 = No Change.
http://onsemi.com
2




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74ALVC16374 flip-flop

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