DM74S174 반도체 회로 부품 판매점
Hex/Quad D Flip-Flop
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 Fairchild Semiconductor |
August 1986
Revised April 2000
DM74S174 • DM74S175
Hex/Quad D Flip-Flop with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop lo gic. All h ave a d irect cle ar
input, and the quad (DM74S175) versions feature comple-
mentary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either th e H IGH or LOW l evel, th e D i nput si gnal has no
effect at the output.
Features
s DM74S174 contain six flip-flops with single-rail outputs.
s DM74S175 con tain fo ur fl ip-flops w ith do uble-rail out-
puts.
s Buffered clock and direct clear inputs
s Individual data input to each flip-flop
s Applications include:
Buffer/storage registers
Shift registers
Pattern generators
s Typical clock frequency 110 MHz
s Typical power dissipation per flip-flop 75mW
Ordering Code:
Order Number
DM74S174N
DM74S175N
Package Number
Package Description
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagrams
DM74S174
DM74S175
© 2000 Fairchild Semiconductor Corporation DS006472
www.fairchildsemi.com
http://www.Datasheet4U.com
Function Table (Each Flip-Flop)
Inputs
Clear
Clock
D
LXX
H ↑H
H↑L
HLX
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care
↑ = Transition from LOW-to-HIGH level
Q0 = The level of Q before the indicated steady-state input conditions were established.
Note 1: DM74S175 only.
Logic Diagrams
DM74S174
Outputs
Q Q (Note 1)
LH
HL
LH
Q0 Q0
DM74S175
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DM74S174 flip-flop
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관련 데이터시트
DM74S174
Hex/Quad D Flip-Flop - Fairchild Semiconductor
DM74S175
Hex/Quad D Flip-Flop - Fairchild Semiconductor