PDF 74AUP2G79 Data sheet ( Hoja de datos )

Número de pieza	74AUP2G79
Descripción	Low-power dual D-type flip-flop
Fabricantes	NXP Semiconductors
Logotipo
Hay una vista previa y un enlace de descarga de 74AUP2G79 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas
No Preview Available ! www.DataSheet4U.com 74AUP2G79 Low-power dual D-type ﬂip-ﬂop; positive-edge trigger Rev. 02 — 19 March 2008 Product data sheet 1. General description The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully speciﬁed for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backﬂow current through the device when it is powered down. The 74AUP2G79 provides the dual positive-edge triggered D-type ﬂip-ﬂop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101-C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD78 Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C 1 page www.DNatXaSPheSete4Um.coicmonductors 74AUP2G79 Low-power dual D-type ﬂip-ﬂop; positive-edge trigger 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Tamb = 25 °C VIH HIGH-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V 0.70 × VCC - 0.65 × VCC - VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 1.6 - 2.0 - VIL LOW-level input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V -- -- VCC = 2.3 V to 2.7 V -- VCC = 3.0 V to 3.6 V -- VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VCC − 0.1 - 0.75 × VCC - 1.11 - 1.32 - 2.05 - 1.9 - 2.72 - 2.6 - VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V - - IO = 1.1 mA; VCC = 1.1 V -- IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V -- -- IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V -- -- IO = 2.7 mA; VCC = 3.0 V -- IO = 4.0 mA; VCC = 3.0 V -- II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - IOFF ∆IOFF power-off leakage current additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - - - ICC ∆ICC supply current additional supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V per pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - [1] - - - CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.6 CO output capacitance VO = GND; VCC = 0 V - 1.3 Max Unit -V -V -V -V 0.30 × VCC V 0.35 × VCC V 0.7 V 0.9 V -V -V -V -V -V -V -V -V 0.1 0.3 × VCC 0.31 0.31 0.31 0.44 0.31 0.44 ±0.1 ±0.2 ±0.2 V V V V V V V V µA µA µA 0.5 µA 40 µA - pF - pF 74AUP2G79_2 Product data sheet Rev. 02 — 19 March 2008 © NXP B.V. 2008. All rights reserved. 5 of 19 5 Page www.DNatXaSPheSete4Um.coicmonductors 74AUP2G79 Low-power dual D-type ﬂip-ﬂop; positive-edge trigger Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions 25 °C −40 °C to +85 °C Min Typ[1] Max Min Max CPD power f = 1 MHz; dissipation VI = GND to VCC capacitance VCC = 0.8 V [3] - 1.6 - - - VCC = 1.1 V to 1.3 V - 1.7 - - - VCC = 1.4 V to 1.6 V - 1.8 - - - VCC = 1.65 V to 1.95 V - 1.9 - - - VCC = 2.3 V to 2.7 V - 2.3 - - - VCC = 3.0 V to 3.6 V - 2.7 - - - −40 °C to +125 °C Unit Min Max -- -- -- -- -- -- pF pF pF pF pF pF [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 12. Waveforms VI nD input GND VI nCP input GND VOH nQ output VOL VM tPHL VM VM tPLH VM 001aaf271 Fig 7. Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. The clock input (nCP) to output (nQ) propagation delays 74AUP2G79_2 Product data sheet Rev. 02 — 19 March 2008 © NXP B.V. 2008. All rights reserved. 11 of 19 11 Page

Páginas	Total 19 Páginas
PDF Descargar	[ Datasheet 74AUP2G79.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
74AUP2G79	Low-power dual D-type flip-flop	NXP Semiconductors

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar